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TPD7203F
TOSHIBA Intelligent Power Device Silicon Monolithic Power MOS Integrated Circuit
TPD7203F
Power MOSFET Gate Driver for 3-Phase DC Motor
The TPD7203F is a power MOSFET gate driver for 3-phase full-bridge circuits that use a charge pump system. The inclusion of a charge pump circuit for high-side drive inside the IC makes it easy to configure a 3-phase full-bridge circuit.
Features
Power MOSFET gate driver for 3-phase DC motor Built-in power MOSFET protection and diagnosis function: low-voltage protection Built-in charge pump circuit Package: SSOP-24 (300 mil) with embossed-tape packing
Pin Assignment
Marking
Weight: 0.29 g (typ.)
Lot No. A dot indicates lead (Pb)-free package or lead (Pb)-free finish.
TPD7203F
Part No. (or abbreviation code)
Due to its MOS structure, this product is sensitive to static electricity.
Handle with care.
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TPD7203F
Block Diagram / Application Circuit
*1: *2: *3: Note:
Optimum conditions depend on the switching loss, EMI, etc., of the external MOSFET. This is a laminated ceramic capacitor. High-speed diode trr = 100 ns max (Recommended: CRH01) For details on selecting external parts, see "Method for selecting external parts" described later.
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Pin Description
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Symbol COSC ROSC IN5 IN6 IN1 IN2 IN3 IN4 FAULT SGND CP1 CP2 VDD WB PGND VB UB WU W VU V UU U CPV Pin Description This pin sets the oscillation frequency for the charge pump drive. Connect a 1500 pF (recommended) capacitor. This pin sets the oscillation frequency for the charge pump drive. Connect a 100 k (recommended) resistor. Input pin: it controls the power MOSFET connected to VB. Built-in pull-down resistor (100 k typ.) Input pin: it controls the power MOSFET connected to WB. Built-in pull-down resistor (100 k typ.) Input pin: it controls the power MOSFET connected to UU. Built-in pull-down resistor (100 k typ.) Input pin: it controls the power MOSFET connected to VU. Built-in pull-down resistor (100 k typ.) Input pin: it controls the power MOSFET connected to WU. Built-in pull-down resistor (100 k typ.) Input pin: it controls the power MOSFET connected to UB. Built-in pull-down resistor (100 k typ.) Diagnosis output pin: when low-voltage 6 V (typ.) is detected, output "H". Circuit configuration is N-ch open drain. Signal block GND pin Capacitor pin for charge pump Connect a 0.47 F (recommended) laminated ceramic capacitor. Capacitor pin for charge pump Connect a 0.47 F (recommended) laminated ceramic capacitor. Power supply pin: when low voltage (6 V typ.) is detected, all outputs are shut down. Drives the power MOSFET connected to the low side of the W phase. Power block GND pin Drives the power MOSFET connected to the low side of the V phase. Drives the power MOSFET connected to the low side of the U phase. Drives the power MOSFET connected to the high side of the W phase. W phase output pin Drives the power MOSFET connected to the high side of the V phase. V phase output pin Drives the power MOSFET connected to the high side of the U phase. U phase output pin Final stage capacitor for the charge pump Connect 1 F (recommended) laminated ceramic capacitor and 10 F (recommended) aluminum electrolytic capacitor in parallel.
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Truth Table
(All outputs go to low for input in high-side/low-side arm shorting mode)
Mode No. 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Input In1 In2 In3 In4 In5 In6 Out (UU) (VU) (WU) (UB) (VB) (WB) UU L H L L L L L H H H L L L L L L H L H L L L H H H L L L H H L L H L L L L L L L H H H L L L H H L L L L H H H H H H L L L L L H L L L L L L L L L H H H L H H L L L L L L H H H H H L L L L H L L H L L H L L H L L L L L H L H H L L H L L H L L L L L L H L L H L L H L L H L L L L H H L L H L L H L L H L L L L L L H L L H L L H L L H L L L L H H L L H L L H L L L H L L L L L L H H L L L L L L H L H L L L L L H L L L L H Out VU L L H L L L L L L L H L H L L L H H L L L L L L H H L L L L Output Out WU L L L H L L L L L L L L L H H L L H H L L L L L L H L L L H Out UB L L L L H L L L L L H L L H L L L L L H L H L L L H L L L L Out VB L L L L L H L L H L L L L L H L L L L H H L L L L L L L L H Out WB L L L L L L H L L H L L H L L L L L L L H H L L H L L L L L High-side/low-side arm shorting mode * High-side/low-side arm shorting mode * High-side/low-side arm shorting mode * High-side/low-side arm shorting mode * High-side/low-side arm shorting mode * High-side/low-side arm shorting mode * 120 square wave conducting normal mode 120 square wave conducting normal mode 120 square wave conducting normal mode High-side/low-side arm shorting mode * 120 square wave conducting normal mode 120 square wave conducting normal mode 120 square wave conducting normal mode High-side/low-side arm shorting mode * Remarks
*:
High-side/low-side arm shorting mode is disabled by the internal logic. (FAULT is kept low.) When undervoltage (6 V typ.) is detected, all outputs are pulled low regardless of input signals. At this time, FAULT output goes high (open-drain, high-impedance).
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Mode No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 53 54 55 56 57 58 59 60 61 62 63 64 Input In1 In2 In3 In4 In5 In6 Out (UU) (VU) (WU) (UB) (VB) (WB) UU H H H H L L L L L L H L H H H L L L H H H H H H L L H H H H L H H L L L L H H H L L L H L H H H H H H L L L H H L H L H H H H H L H H L L L L L L H H H H L L L L H H H H H H H H L L H H H H L H H H L H L H H L H H L H L H H L H H L H H L H L L H H H H L H H H H H L H H L H H L H H L L H H H L H H L H H L H L H H H H H L H H H H H L H H L H H L H H L H L H H L H H L H H L H H H H L H H H H H H L L H L L L L L L L H L L L L L L L L L L L L L L L L L L L L L L Out VU L L L L L L H L L L H L L L L L L L L L L L L L L L L L L L L L L Output Out WU L L L L L L L H L L H L L L L L L L L L L L L L L L L L L L L L L Out UB L L L L L L H H L L L H L L L L L L L L L L L L L L L L L L L L L Out VB L L H L L L L H L L L H L L L L L L L L L L L L L L L L L L L L L Out WB L L H L L L H L L L L H L L L L L L L L L L L L L L L L L L L L L High-side/low-side arm shorting mode * High-side/low-side arm shorting mode * High-side/low-side arm shorting mode * High-side/low-side arm shorting mode * High-side/low-side arm shorting mode * High-side/low-side arm shorting mode * High-side/low-side arm shorting mode * High-side/low-side arm shorting mode * High-side/low-side arm shorting mode * High-side/low-side arm shorting mode * High-side/low-side arm shorting mode * High-side/low-side arm shorting mode * High-side/low-side arm shorting mode * High-side/low-side arm shorting mode * High-side/low-side arm shorting mode * High-side/low-side arm shorting mode * High-side/low-side arm shorting mode * High-side/low-side arm shorting mode * High-side/low-side arm shorting mode * High-side/low-side arm shorting mode * High-side/low-side arm shorting mode * High-side/low-side arm shorting mode * High-side/low-side arm shorting mode * High-side/low-side arm shorting mode * High-side/low-side arm shorting mode * High-side/low-side arm shorting mode * Remarks
High-side/low-side arm shorting mode * High-side/low-side arm shorting mode *
*:
High-side/low-side arm shorting mode is disabled by the internal logic. (FAULT is kept low.) When undervoltage (6 V typ.) is detected, all outputs are pulled low regardless of input signals. At this time, FAULT output goes high (open-drain, high-impedance).
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Absolute Maximum Ratings (Ta = 25C)
Characteristic Power supply voltage Output current Input voltage Fault pin voltage U, V and pin negative voltage Symbol VDD ISOURCE ISINK VIN VFAULT U (-) V (-) W (-) PGND(-) IFAULT PD Topr Tstg Rating - 0.5 ~ 30 1 1 - 0.5 ~ 7.0 30 - 0.5 Unit V A V V V Negative voltage that can be applied to U, V and W pins (Reference to SGND pin) Negative voltage that can be applied to PGND pin (reference to SGND pin) Pulse width 10s Remarks
PGND pin negative voltage Fault pin current Power dissipation Operating temperature Storage temperature
- 0.5 5 0.8 1.2 Note
V mA W C C
- 40 ~ 125 - 40 ~ 150
Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook ("Handling Precautions"/Derating Concept and Methods) and individual reliability data (i.e. reliability test report and estimated failure rate, etc).
Thermal Resistance
Characteristic Junction to ambient thermal resistance Symbol Rth (j-a) Rating 156.3 104.2 Note Unit C / W
Note:
When the device is mounted on a 60 mm x 60 mm x 1.6 mm glass epoxy PCB
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TPD7203F
Electrical Characteristics
Characteristic Operating supply voltage Symbol VDD IDD(1) Supply current IDD(2) VIH Input voltage VIL IIH Input current IIL 2 2
(Unless otherwise specified, Ta = -40 ~ 125C)
Test Circuit 1 2 Condition VDD = 13.5 V VDD = 13.5 V, VIN1 ~ VIN6 =0V VDD = 7 ~ 18 V, IO = 0 A VDD = 7 ~ 18 V, VIN = 5 V, IO = 0 A VDD = 7 ~ 18 V, VIN = 0 V, IO = 0 A VDD = 13.5 V, VIN = 5 V, IO = 0 A Min 7 Typ. 13.5 Max 18 10 100 V 1.5 mA Unit V Oscillation circuit stops When oscillation circuit is operating f = 20 kHz, mean current IN1- IN6 high-level input voltage IIN1-IN6 low-level input voltage Remarks
3.5
1
mA IN1-IN6 input current
- 10
10
A VCPV denotes CPV pin voltage. (reference to SGND pin) UU pin voltage (reference to U pin) VU pin voltage (reference to V pin) WU pin voltage (reference to W pin) UB pin voltage (reference to PGND pin) VB pin voltage (reference to PGND pin) WB pin voltage (reference to PGND pin) V CPV pin voltage (reference to SGND pin) UB, VB and WB pins clamp voltage (reference to PGND pin)
VOH High side VOL 2
VCPV -2
VCPV
Output voltage
VDD = 13.5 V, VIN = 0 V, IO = 0 A VDD = 13.5 V, VIN = 5 V, IO = 0 A VDD = 13.5 V, VIN = 0 V, IO = 0 A
0.1 V
VOH Low side VOL Charge pump voltage Active clamp voltage (low side) VCPV VCLAMP 2
11.5
13.5

0.1
VDD = 13.5 V VIN = 5 V, IO = 10 mA VDD = 13.5 V, VIN = 5 V, IO = 0.5 A VDD = 13.5 V, VIN = 0 V, IO = 0.5 A
30
35
18
V
RSOURCE Output ON resistance RSINK 2
7
10
4.5
10
UU, VU, WU, UB, VB and WB output resistance pulse width10 s
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TPD7203F
Characteristic Lowvoltage protection Detection Hysteresis Turn-on delay time Switching time Turn-on time Turn-off delay time Turn-off time Oscillating frequency Symbol VSD (L) VSD (L) td (ON) tON 4 td (OFF) tOFF fosc VFAULT tON Fault delay time tOFF 3 2 VDD = 7 ~ 18 V, ROSC = 100 k, COSC = 1500 pF IFAULT = 1 mA RFAULT = 5.1 k, VFAULT = 5 V (External power supply) Test Circuit 3 Condition Min 5.5 Typ. 6 0.5 Max 6.5 4 Unit Remarks Low voltage detection voltage and hysteresis (VDD voltage detected)
V
VDD = 7 to 18 V, COUT = 0.047F, RG = 47
6 s 4
UU, VU, WU, UB, VB and WB switching time
6 fOSC calculation formula fOSC 3 / {COSC (ROSC + 2 k)} (Hz) FAULT pin low-level voltage (open - drain) Time from low voltage / overvoltage detection or restoration to FAULT output inversion
20 1 1
kHz
Fault pin voltage
2
0.8
V
s
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TPD7203F
Test Circuit 1
IDD(1)
Testing Circuit 2
IDD(2), VIH, VIL, IIH, IIL, VOH, VOL, VCPV, VFAULT
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Testing Circuit 3 VSD(L), VSD, VSD(H), VSD(H), FAULT delay time tON, tOFF
Low voltage
Low voltage
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Testing Circuit 4
td(ON), tON, td(OFF), tOFF
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TPD7203F
IDD(1)
-
Ta
IDD(1)
-
Ta
AMBIENT TEMPERATURE
Ta
()
AMBIENT TEMPERATURE
Ta
()
Ta=25
Ta=25
VIH
-
Ta
VIL -
Ta
AMBIENT TEMPERATURE
Ta
()
AMBIENT TEMPERATURE
Ta
()
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TPD7203F
IIH
-
Ta
IIL -
Ta
AMBIENT TEMPERATURE
Ta
()
AMBIENT TEMPERATURE
Ta
()
Ta=25, IO=0A
Ta=25
VDROP
-
Ta
VOL
-
Ta
AMBIENT TEMPERATURE
Ta
()
AMBIENT TEMPERATURE
Ta
()
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TPD7203F
RSOURCE
-
Ta
RSINK
-
Ta
AMBIENT TEMPERATURE
Ta
()
AMBIENT TEMPERATURE
Ta
()
VSD(L)
-
Ta
VSD(L)
-
Ta
AMBIENT TEMPERATURE
Ta
()
AMBIENT TEMPERATURE
Ta
()
Ta=25
Ta=25
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TPD7203F
tON - Ta
tOFF- Ta
AMBIENT TEMPERATURE
Ta
()
AMBIENT TEMPERATURE
Ta
()
fOSC
-
Ta
VFAULT
-
Ta
AMBIENT TEMPERATURE
Ta
()
AMBIENT TEMPERATURE
Ta
()
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Method for Selecting External Parts
Pin No. 1 2 11 12 Pin Name COSC ROSC CP1 CP2 Type Capacitor Resistor Capacitor Recommended Value / Recommended Product 1500 pF (ceramic) 100 k 0.47 F (laminated ceramic ) 1 F (laminated ceramic) and 10 F (aluminum electrolytic ) connected in parallel Description Sets the charge pump oscillation frequency. Sets the charge pump oscillation frequency. Capacitor for the charge pump: The greater this capacitance, the larger the charging current to the capacitor and the greater the loss in the IC. The greater this capacitance, the larger the current supply capacity of the charge pump (CPV pin) but the greater the loss in the IC. Take care not to exceed the allowable loss. Diode for the charge pump. An electric charge equal to the diode's Qrr component goes out of the capacitor's charged electricity. Therefore, use a high-speed diode. Diode for the charge pump An electric charge equal to the Qrr component of the diode goes out of the electrical charge of the capacitor. Therefore use a high-speed diode.
24
CPV
Capacitor
11 12 24
CP1 CP2 CPV
High-speed iode
trr = 100 ns (max) CRH01 (trr = 35 ns max) recommended
22 20 18 17 16 14
UU VU WU UB VB WB
Resistor
Gate resistor for external power MOSFET. Choose the optimum value by considering the switching loss and EMI of the power MOSFET.
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Usage Precautions
Note 1: Feeding the charge pump voltage to external devices Current can be taken out of the final stage (CPV pin) of the charge pump and fed to external devices without causing any problem. In this case, because the charge pump voltage drops, increase the capacitance of the capacitor connected to the CPV pin. However, this will cause the charging current to the capacitor and, hence, loss in the IC to increase. Therefore be careful not to exceed the allowable loss. Note 2: Heat sink design Because this IC contains a charge pump function, loss in it affects external capacitor capacitance and diode characteristics. It is recommended that the junction temperature, Tj, be judged from the on-voltage of the FAULT pin (open-drain). When VDD is within the range of operating power supply voltages, the FAULT pin outputs a low. For details about on-voltage characteristics, see Tj-VFAULT characteristic curves. Note 3: Dead time setting For arm-shorting input logic, all outputs (UU, VU, WU, UB, VB and WB) are pulled low. When operating in forward or reverse mode, take into account the IC output switching time and the switching time (including temperature characteristic) of the external power MOSFET when setting the dead time. The dead time required for only the IC, not including the external power MOSFET, is 4s (within all operating power supply voltages and all operating temperatures). Note 4: Shorting between outputs, short-circuit of outputs and VDD pin or short-circuit of outputs and GND pin may cause the IC to break down. Therefore, pay careful attention to the design of output lines and VDD and GND lines. Precautions on dry packing After unpacking dry or moisture-proof packing, make sure the device is mounted in place within 48 hours at a temperature and humidity of 30C and 60% RH or less. Because the device is emboss-taped and cannot be processed by baking, always be sure to use it within the said allowable time after unpacking. Standard tape packing quantity: 2000 devices / reel (EL1).
Note 5:
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Package Dimensions
Unit: mm
Weight: 0.29 g (typ.)
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RESTRICTIONS ON PRODUCT USE
* The information contained herein is subject to change without notice.
20070701-EN
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.).These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in his document shall be made at the customer's own risk. * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. * Please contact your sales representative for product-by-product details in this document regarding RoHS compatibility. Please use these products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations.
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